The sent invention relates to a semiconductor memory device including a capacitor having a large capacitance and a related method of manufacturing such a memory device. In particular, the present invention is directed to a semiconductor memory cell capacitor including a roughened refractory metal or metal silicide film.
Dynamic random access memories (DRAMs) are well known semiconductor memories which typically include an array of memory cells. Each memory cell includes an active element, such as a transistor, and a capacitor. As integration density increases, the area on the surface of a semiconductor chip available for each memory cell decreases. In addition, design rules, which dictate the layout of the DRAM, allocate space exclusively for the transistor in each memory cell, thereby further limiting the surface area available for forming the capacitor.
On the other hand, it is necessary for the effective area of the capacitor to be as large as possible. This is because capacitance increases with increasing capacitor area. Accordingly, efforts have been made to fabricate three-dimensional capacitor structures to increase the effective area of the memory cell capacitor. These three-dimensional structures include stacked structures, trenched structures, cylindrical structures and finned structures. These structures, however, are complicated, typically difficult to fabricate, and suffer from poor reliability.
The capacitance of the capacitor memory cell may also be increased by reducing the thickness of the capacitor dielectric. Thus, research into the development of future generations of DRAMs has focused, in part, on fabricating very thin dielectric films because it is expected that 256M DRAMs, for example, will have a capacitor dielectric thickness of about 3 nm (assuming that the dielectric is an oxide film such as silicon dioxide).
An oxide-nitride-oxide (ONO) film has been proposed for use in three-dimensional capacitor structures. Although ONO has a relatively high dielectric constant, it is not high enough to be used in the miniaturized capacitors of future DRAM memory cells. Moreover, experiments have shown that ONO films cannot be made thinner than 4 nanometers. (See P. J. Wright and K. C. Saraswat, xe2x80x9cThickness Limitation of SiO2 Gate Dielectrics for MOS ULSIxe2x80x9d, IEEE Transactions on Electric Devices, Volume 37, No. 8, 1990). Accordingly, capacitors including ONO dielectric films must have a complicated three-dimensional structure in order to obtain a sufficient capacitance and the resulting capacitance may still be insufficient if the capacitor is small. Such complex capacitor structures, such as the stacked structures, have poor topology, while other structures, such as cylindrical and finned capacitor geometries, require a high degree of planarization. Although such planarization can be achieved, it is obtained at the expense of having to form buried contacts of different depths during subsequent wire forming process steps.
Trench capacitors have also been proposed to provide an increased capacitance. These structures, however, have a high aspect ratio, thereby making them difficult to etch and clean. In addition, it is difficult to provide a buried silicon capacitor electrode in a trench.
Two solutions to the above described problems have been proposed. The first involves forming the storage node or capacitor using HSG-Si (hemispherical grained silicon). HSG-Si has a relatively rough morphology as opposed to conventional silicon surfaces, which can be made quite smooth by altering the chemical vapor deposition (CVD) process used for making polycrystalline silicon. Specifically, instead of depositing polycrystalline silicon at a temperature over 600xc2x0 C., hemispherical silicon grain projections are formed by performing the deposition at 550xc2x0 C. Alternatively, the standard CVD deposition of polycrystalline silicon can be used, followed by heat treatment within the range of 580 to 600xc2x0 C. A capacitor storage node formed of HSG-Si will have an effective capacitor area which is approximately 1.8 to 2.0 times that of a comparable storage node having a smooth silicon layer. It is thus a candidate for making capacitors in a smaller area limited by design rules. Although high quality HSG-Si films have been grown, such films are not suitable for use in conjunction with the ONO dielectric films described above. This is because the resulting capacitor structure has a capacitance of only 9.1 fF/mm2. This is the case even with variations in topology in the range of 0.8 mm. Accordingly, a complicated capacitor structure must still be formed in order to obtain sufficient of the memory cell capacitance.
According to a second approach, films having a large dielectric constant CR have been proposed for use in capacitors of DRAM memory cells. These films include Ta2O5 (tantalum pentaoxide) xcex5R=24), PZT (lead zirconate, titanate) xcex5R=2000), and BST (barium strontium titanate) (xcex5R=3000).
For example, tantalum pentaoxide is frequently deposited by low pressure chemical vapor deposition (LPCVD), plasma enhanced (CVD or electron cyclotron resonance (ECR). In each of these methods, penta-ethoxy-tantalum Ta(OC2H5)5 and oxygen are introduced into a reaction chamber. The penta-ethoxy-tantalum serves as a source for Ta to be oxidized by the oxygen. Tantalum pentaoxide has a dielectric constant within the range of 22 to 28, which is more than 6 times greater than silicon dioxide. In addition, when subjected to an appropriate heat treatment, the tantalum pentaoxide film has a relatively low leakage current of about 10xe2x88x929 to 10xe2x88x927 A/cm2 under an electric field of 4 MV/cm. Accordingly, tantalum pentaoxide would appear to be a prime candidate for a thin film capacitor dielectric in future DRAMs.
Unfortunately, when tantalum pentaoxide is deposited on silicon, oxygen reacts with the underlying silicon layer, thereby forming a thin layer of silicon dioxide. This silicon dioxide layer grows thicker during the above described heat treatment of the tantalum pentaoxide layer. Since silicon dioxide has a lower dielectric constant than tantalum pentaoxide, the effective dielectric constant of the combined silicon dioxide/tantalum pentaoxide layer is significantly lower than that of tantalum pentaoxide alone.
Recently, it has been proposed to deposit an intermediate layer of silicon nitride to prevent formation of silicon dioxide during the deposition of tantalum pentaoxide. This silicon nitride layer is formed by nitridation of the surface of the silicon storage node prior to deposition of the tantalum pentaoxide layer. The resulting film has an improved dielectric constant, as well as leakage current. (See Satoshi Kamiyana, Piere-Yves Lesaicherre, Akihiko Ishitani, Akir Sakai, Akio Tanikawa and Iwao Nishiyama, Extended Abstracts of the 1992 International Conference on Solid State Devices and Materials, Tskuba, pp. 521-523, 1992, and P. C. Fazan, V. K. Mathews, R. J. Maddox, A. Ditali, N. Sandler, and D. L. Kwong, Extended Abstracts of the 1992 International Conference on Solid State Devices of Materials, Tskuba, pp. 697-698, 1992).
It has further been proposed to deposit tantalum pentaoxide on a rough silicon surface serving as a capacitor electrode. The resulting storage node has a capacitance which is 70% higher than that associated with smooth silicon and has good reliability. (See H. Watanabe, T. Tatsumi, T. Niino, A. Sakai, N. Aoto, K. Koyama and T. Kikkawa, Extended Abstracts of the 1991 International Conference on Solid Devices and Materials, Yokohama, pp. 478-480). The technique used to fabricate this structure, however, will become practical only when high capacitances (e.g., 12.5 sfF/mm2) become reproducible.
Moreover, so long as the tantalum pentaoxide film is deposited on a silicon capacitor underside electrode, silicon dioxide will be formed during the tantalum pentaoxide deposition. Accordingly, an intermediate silicon nitride layer must be deposited prior to the tantalum pentaoxide deposition. This is the case whether the silicon underside electrode is rough or not. It is therefore undesirable to deposit tantalum pentaoxide on silicon. Moreover, other materials, such as PZT and BST suffer from reduced dielectric constants as well as high leakage currents when they are made as thin films.
An object of the present invention is to provide a memory cell having a capacitor with a large capacitance. An additional object of the present invention is to provide a capacitor having a large effective area for use in a DRAM memory cell.
These and other objects and features of this invention can be achieved by a method of forming a rough or rugged tungsten film comprising the steps of: forming a TiN film on a semiconductor substrate; and depositing tungsten on the TiN film at a temperature in a range of 200xc2x0-650xc2x0 C.
Further, in accordance with the present invention, a semiconductor device is provided comprising: a substrate having a primary surface; a first layer, including TiN, formed on the primary surface of said substrate; and a second layer including tungsten formed on the first layer, wherein the second layer further includes a plurality of recessed portions and a plurality of elevated portions adjacent the recessed portions.
In accordance with the present invention, a rough or rugged tungsten film is provided on a lower silicon capacitor electrode in a DRAM memory cell. Since the tungsten film is rough, the effective area of the capacitor in the memory cell is increased. In addition, a high dielectric constant thin film can be readily deposited on the rough tungsten film to further increase the capacitance of the memory cell capacitor.